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ASCON-128 finalist from the CAESAR competition
This commit is contained in:
Rhys Weatherley
520
gen/genascon.c
Normal file
520
gen/genascon.c
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@@ -0,0 +1,520 @@
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/*
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* Copyright (C) 2018 Southern Storm Software, Pty Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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// Special-purpose compiler that generates the AVR version of Ascon128.
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#include <stdio.h>
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#include <stdarg.h>
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#include <stdlib.h>
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static int indent = 4;
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static const int temp_reg = 0; // Register number for the AVR "__tmp_reg__".
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// Registers that can be used for temporary values, in the best
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// order to allocate them. High registers are listed first.
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static int regs[] = {
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16, 17, 18, 19, 20, 21, 22, 23, 7, 8, 9, 10, 11, 12, 13, 14, 15
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};
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#define num_regs (sizeof(regs) / sizeof(regs[0]))
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// Which registers are currently in use?
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static int reg_in_use[num_regs] = {0};
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// Which registers did we use while generating the code?
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static int reg_used[num_regs] = {0};
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// Information about a set of registers storing a 64-bit quantity.
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typedef struct
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{
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int first; // First register in the set for 8-bit rotates.
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int reg[8]; // Register numbers.
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} Reg64;
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// Indent the code and print a string.
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void indent_printf(const char *format, ...)
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{
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va_list va;
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int posn;
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va_start(va, format);
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for (posn = 0; posn < indent; ++posn)
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putc(' ', stdout);
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vfprintf(stdout, format, va);
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va_end(va);
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}
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// Print an assembler instruction within quotes.
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void insn_printf(const char *format, ...)
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{
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va_list va;
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int posn;
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va_start(va, format);
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for (posn = 0; posn < indent; ++posn)
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putc(' ', stdout);
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putc('"', stdout);
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vfprintf(stdout, format, va);
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putc('\\', stdout);
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putc('n', stdout);
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putc('"', stdout);
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putc('\n', stdout);
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va_end(va);
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}
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// Allocate an unused register, starting with high registers.
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void alloc_high_reg(int *reg)
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{
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unsigned index;
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if (*reg != -1) {
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fprintf(stderr, "Temporary register wasn't previously released\n");
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exit(1);
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}
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for (index = 0; index < num_regs; ++index) {
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if (!reg_in_use[index]) {
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reg_in_use[index] = 1;
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reg_used[index] = 1;
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*reg = regs[index];
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if (*reg < 16) {
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fprintf(stderr, "Ran out of temporary high registers\n");
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exit(1);
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}
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return;
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}
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}
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fprintf(stderr, "Ran out of temporary registers\n");
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exit(1);
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}
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// Allocate an unused register, starting with low registers
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// because we know we won't need the value in a high reg later.
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static void alloc_low_reg(int *reg)
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{
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unsigned index;
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if (*reg != -1) {
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fprintf(stderr, "Temporary register wasn't previously released\n");
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exit(1);
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}
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for (index = num_regs; index > 0; --index) {
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if (!reg_in_use[index - 1]) {
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reg_in_use[index - 1] = 1;
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reg_used[index - 1] = 1;
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*reg = regs[index - 1];
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return;
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}
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}
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fprintf(stderr, "Ran out of temporary registers\n");
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exit(1);
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}
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// Release a register back to the allocation pool.
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static void release_reg(int *reg)
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{
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unsigned index;
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for (index = 0; index < num_regs; ++index) {
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if (regs[index] == *reg && reg_in_use[index]) {
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reg_in_use[index] = 0;
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*reg = -1;
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return;
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}
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}
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fprintf(stderr, "Released a register that was not in use\n");
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exit(1);
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}
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// Check that we have a high register when we need one.
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void check_high_reg(int *reg)
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{
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if ((*reg) < 16) {
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fprintf(stderr, "r%d is not a high register\n", *reg);
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exit(1);
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}
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}
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// Check that all temporary registers have been released.
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static void check_regs(void)
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{
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unsigned index;
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for (index = 0; index < num_regs; ++index) {
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if (reg_in_use[index]) {
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fprintf(stderr, "Register r%d has not been released\n",
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regs[index]);
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exit(1);
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}
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}
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}
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// Allocate a 64-bit register set.
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static void alloc_reg64(Reg64 *reg)
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{
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reg->first = 0;
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reg->reg[0] = -1;
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reg->reg[1] = -1;
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reg->reg[2] = -1;
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reg->reg[3] = -1;
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reg->reg[4] = -1;
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reg->reg[5] = -1;
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reg->reg[6] = -1;
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reg->reg[7] = -1;
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alloc_low_reg(&(reg->reg[0]));
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alloc_low_reg(&(reg->reg[1]));
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alloc_low_reg(&(reg->reg[2]));
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alloc_low_reg(&(reg->reg[3]));
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alloc_low_reg(&(reg->reg[4]));
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alloc_low_reg(&(reg->reg[5]));
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alloc_low_reg(&(reg->reg[6]));
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alloc_low_reg(&(reg->reg[7]));
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}
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// Release a 64-bit register set.
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static void release_reg64(Reg64 *reg)
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{
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release_reg(&(reg->reg[0]));
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release_reg(&(reg->reg[1]));
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release_reg(&(reg->reg[2]));
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release_reg(&(reg->reg[3]));
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release_reg(&(reg->reg[4]));
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release_reg(&(reg->reg[5]));
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release_reg(&(reg->reg[6]));
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release_reg(&(reg->reg[7]));
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}
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#define REGn(r, n) ((r)->reg[((n) + (r)->first) % 8])
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// Rotate a 64-bit register left by 1 bit.
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static void rotate_reg64_left_1(Reg64 *reg)
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{
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insn_printf("lsl r%d", REGn(reg, 0));
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insn_printf("rol r%d", REGn(reg, 1));
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insn_printf("rol r%d", REGn(reg, 2));
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insn_printf("rol r%d", REGn(reg, 3));
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insn_printf("rol r%d", REGn(reg, 4));
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insn_printf("rol r%d", REGn(reg, 5));
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insn_printf("rol r%d", REGn(reg, 6));
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insn_printf("rol r%d", REGn(reg, 7));
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insn_printf("adc r%d,__zero_reg__", REGn(reg, 0));
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}
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// Rotate a 64-bit register left by 8 bits.
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static void rotate_reg64_left_8(Reg64 *reg)
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{
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reg->first = (reg->first + 7) % 8;
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}
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// Rotate a 64-bit register right by 1 bit.
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static void rotate_reg64_right_1(Reg64 *reg)
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{
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insn_printf("bst r%d,0", REGn(reg, 0));
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insn_printf("ror r%d", REGn(reg, 7));
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insn_printf("ror r%d", REGn(reg, 6));
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insn_printf("ror r%d", REGn(reg, 5));
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insn_printf("ror r%d", REGn(reg, 4));
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insn_printf("ror r%d", REGn(reg, 3));
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insn_printf("ror r%d", REGn(reg, 2));
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insn_printf("ror r%d", REGn(reg, 1));
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insn_printf("ror r%d", REGn(reg, 0));
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insn_printf("bld r%d,7", REGn(reg, 7));
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}
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// Rotate a 64-bit register right by 8 bits.
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static void rotate_reg64_right_8(Reg64 *reg)
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{
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reg->first = (reg->first + 1) % 8;
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}
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// Rotate a 64-bit register right by a number of bits.
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static void rotate_reg64_right(Reg64 *reg, int bits)
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{
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int bytes;
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if ((bits % 8) < 4) {
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// Rotate in the right direction.
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bytes = bits / 8;
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while (bytes > 0) {
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rotate_reg64_right_8(reg);
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--bytes;
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}
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bits %= 8;
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while (bits > 0) {
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rotate_reg64_right_1(reg);
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--bits;
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}
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} else {
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// Quicker to rotate in the left direction.
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bits = 64 - bits;
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bytes = bits / 8;
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while (bytes > 0) {
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rotate_reg64_left_8(reg);
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--bytes;
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}
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bits %= 8;
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while (bits > 0) {
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rotate_reg64_left_1(reg);
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--bits;
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}
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}
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}
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// Load a 64-bit register from a Z pointer offset.
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static void load_reg64(Reg64 *reg, int offset)
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{
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int index;
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for (index = 0; index < 8; ++index, ++offset) {
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if (offset != 0)
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insn_printf("ldd r%d,Z+%d", REGn(reg, index), offset);
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else
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insn_printf("ld r%d,Z", REGn(reg, index));
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}
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}
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// Store a 64-bit register to a Z pointer offset.
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static void store_reg64(Reg64 *reg, int offset)
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{
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int index;
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for (index = 0; index < 8; ++index, ++offset) {
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if (offset != 0)
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insn_printf("std Z+%d,r%d", offset, REGn(reg, index));
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else
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insn_printf("st Z,r%d", REGn(reg, index));
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}
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}
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// Copy one 64-bit register into another.
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static void copy_reg64(Reg64 *dst, Reg64 *src)
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{
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int index;
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for (index = 0; index < 8; ++index)
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insn_printf("mov r%d,r%d", REGn(dst, index), REGn(src, index));
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}
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// XOR two 64-bit registers.
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static void xor_reg64(Reg64 *dst, Reg64 *src)
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{
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int index;
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for (index = 0; index < 8; ++index)
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insn_printf("eor r%d,r%d", REGn(dst, index), REGn(src, index));
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}
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// Print the names of the temporary registers that we used.
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static void temp_regs(void)
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{
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unsigned index;
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int first = 1;
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indent_printf(": ");
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for (index = 0; index < num_regs; ++index) {
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if (reg_used[index]) {
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if (first) {
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first = 0;
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printf("\"r%d\"", regs[index]);
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} else {
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printf(", \"r%d\"", regs[index]);
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}
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}
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}
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printf(", \"memory\"\n");
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}
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// Handle one byte within the substitution layer.
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static void substitute(int offset, int reg)
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{
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int x0 = -1;
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int x1 = -1;
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int x2 = reg;
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int x3 = -1;
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int x4 = -1;
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int t0 = -1;
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int t1 = -1;
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int t2 = -1;
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int t3 = -1;
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int t4 = -1;
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// Allocate five temporary registers for the five words.
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// When processing the zero byte, we already have x2 loaded.
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alloc_low_reg(&x0);
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alloc_low_reg(&x1);
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if (reg == -1)
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alloc_low_reg(&x2);
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alloc_low_reg(&x3);
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alloc_low_reg(&x4);
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// Need five more registers for intermediate results.
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alloc_low_reg(&t0);
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alloc_low_reg(&t1);
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alloc_low_reg(&t2);
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alloc_low_reg(&t3);
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alloc_low_reg(&t4);
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// Read the five bytes from the state.
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if (offset != 0)
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insn_printf("ldd r%d,Z+%d", x0, offset);
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else
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insn_printf("ld r%d,Z", x0);
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insn_printf("ldd r%d,Z+%d", x1, 8 + offset);
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if (reg == -1)
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insn_printf("ldd r%d,Z+%d", x2, 16 + offset);
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insn_printf("ldd r%d,Z+%d", x3, 24 + offset);
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insn_printf("ldd r%d,Z+%d", x4, 32 + offset);
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// Mix the bytes together.
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// x0 ^= x4; x4 ^= x3; x2 ^= x1;
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// t0 = ~x0; t1 = ~x1; t2 = ~x2; t3 = ~x3; t4 = ~x4;
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// t0 &= x1; t1 &= x2; t2 &= x3; t3 &= x4; t4 &= x0;
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// x0 ^= t1; x1 ^= t2; x2 ^= t3; x3 ^= t4; x4 ^= t0;
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// x1 ^= x0; x0 ^= x4; x3 ^= x2; x2 = ~x2;
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insn_printf("eor r%d,r%d", x0, x4);
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insn_printf("eor r%d,r%d", x4, x3);
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insn_printf("eor r%d,r%d", x2, x1);
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||||
insn_printf("mov r%d,r%d", t0, x0);
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||||
insn_printf("com r%d", t0);
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insn_printf("and r%d,r%d", t0, x1);
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||||
insn_printf("mov r%d,r%d", t1, x1);
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||||
insn_printf("com r%d", t1);
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insn_printf("and r%d,r%d", t1, x2);
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||||
insn_printf("mov r%d,r%d", t2, x2);
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||||
insn_printf("com r%d", t2);
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insn_printf("and r%d,r%d", t2, x3);
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||||
insn_printf("mov r%d,r%d", t3, x3);
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||||
insn_printf("com r%d", t3);
|
||||
insn_printf("and r%d,r%d", t3, x4);
|
||||
insn_printf("mov r%d,r%d", t4, x4);
|
||||
insn_printf("com r%d", t4);
|
||||
insn_printf("and r%d,r%d", t4, x0);
|
||||
insn_printf("eor r%d,r%d", x0, t1);
|
||||
insn_printf("eor r%d,r%d", x1, t2);
|
||||
insn_printf("eor r%d,r%d", x2, t3);
|
||||
insn_printf("eor r%d,r%d", x3, t4);
|
||||
insn_printf("eor r%d,r%d", x4, t0);
|
||||
insn_printf("eor r%d,r%d", x1, x0);
|
||||
insn_printf("eor r%d,r%d", x0, x4);
|
||||
insn_printf("eor r%d,r%d", x3, x2);
|
||||
insn_printf("com r%d", x2);
|
||||
|
||||
// Write the five bytes back to the state.
|
||||
if (offset != 0)
|
||||
insn_printf("std Z+%d,r%d", offset, x0);
|
||||
else
|
||||
insn_printf("st Z,r%d", x0);
|
||||
insn_printf("std Z+%d,r%d", 8 + offset, x1);
|
||||
insn_printf("std Z+%d,r%d", 16 + offset, x2);
|
||||
insn_printf("std Z+%d,r%d", 24 + offset, x3);
|
||||
insn_printf("std Z+%d,r%d", 32 + offset, x4);
|
||||
|
||||
// Release the temporary registers.
|
||||
release_reg(&x0);
|
||||
release_reg(&x1);
|
||||
if (reg == -1)
|
||||
release_reg(&x2);
|
||||
release_reg(&x3);
|
||||
release_reg(&x4);
|
||||
release_reg(&t0);
|
||||
release_reg(&t1);
|
||||
release_reg(&t2);
|
||||
release_reg(&t3);
|
||||
release_reg(&t4);
|
||||
}
|
||||
|
||||
static void diffuse(int n, int shift1, int shift2)
|
||||
{
|
||||
Reg64 x, t;
|
||||
int offset = n * 8;
|
||||
|
||||
// Allocate the temporary registers that we need.
|
||||
alloc_reg64(&x);
|
||||
alloc_reg64(&t);
|
||||
|
||||
// Read the 64-bit word into the x registers.
|
||||
load_reg64(&x, offset);
|
||||
|
||||
// Rotate step 1: t = x >>> shift1, t ^= x
|
||||
copy_reg64(&t, &x);
|
||||
rotate_reg64_right(&t, shift1);
|
||||
xor_reg64(&t, &x);
|
||||
|
||||
// Rotate step 2: x = x >>> shift2, x ^= t
|
||||
rotate_reg64_right(&x, shift2);
|
||||
xor_reg64(&x, &t);
|
||||
|
||||
// Store the 64-bit result back to the state.
|
||||
store_reg64(&x, offset);
|
||||
|
||||
// Release the temporary registers.
|
||||
release_reg64(&x);
|
||||
release_reg64(&t);
|
||||
}
|
||||
|
||||
static void permute(void)
|
||||
{
|
||||
int reg = -1;
|
||||
|
||||
// Print the function header.
|
||||
printf("void Ascon128::permute(uint8_t first)\n");
|
||||
printf("{\n");
|
||||
indent_printf("// AVR version generated by the genascon tool.\n");
|
||||
indent_printf("__asm__ __volatile__ (\n");
|
||||
indent += 4;
|
||||
|
||||
// Output the top of the loop.
|
||||
insn_printf("1:");
|
||||
|
||||
// XOR the low byte of x2 with the round constant.
|
||||
alloc_low_reg(®);
|
||||
insn_printf("ldd r%d,Z+16", reg);
|
||||
insn_printf("eor r%d,%%1", reg);
|
||||
|
||||
// Substitution layer. Mix the words one byte at a time.
|
||||
// For the first byte we already have x2 loaded into "reg".
|
||||
substitute(0, reg);
|
||||
release_reg(®);
|
||||
substitute(1, -1);
|
||||
substitute(2, -1);
|
||||
substitute(3, -1);
|
||||
substitute(4, -1);
|
||||
substitute(5, -1);
|
||||
substitute(6, -1);
|
||||
substitute(7, -1);
|
||||
|
||||
// Linear diffusion layer.
|
||||
diffuse(0, 19, 28);
|
||||
diffuse(1, 61, 39);
|
||||
diffuse(2, 1, 6);
|
||||
diffuse(3, 10, 17);
|
||||
diffuse(4, 7, 41);
|
||||
|
||||
// Output the bottom of the loop.
|
||||
insn_printf("subi %%1,0x0F");
|
||||
insn_printf("cpi %%1,0x3C");
|
||||
insn_printf("breq 2f");
|
||||
insn_printf("rjmp 1b");
|
||||
insn_printf("2:");
|
||||
|
||||
// Declare the registers that we need.
|
||||
indent_printf(":: \"z\"(state.S), \"d\"((uint8_t)(0xF0 - (first << 4) + first))\n");
|
||||
temp_regs();
|
||||
indent -= 4;
|
||||
indent_printf(");\n");
|
||||
printf("}\n\n");
|
||||
check_regs();
|
||||
}
|
||||
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
permute();
|
||||
return 0;
|
||||
}
|
||||
Reference in New Issue
Block a user