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Page faults occurring on RO pages with the CopyOnWrite flag set will be handled by the page handler as follows: - allocate new frame - establish temporary mapping for new frame - copy original page to new frame - update entry for the page where the fault occurred: - set physical frame address to the allocated frame - clear CoW flag and set Present, RW flags - return from the fault handler to resume execution at the instruction that caused the fault Any other page faults will still cause a kernel panic
90 lines
2.7 KiB
Go
90 lines
2.7 KiB
Go
// +build amd64
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package vmm
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import "math"
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const (
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// pageLevels indicates the number of page levels supported by the amd64 architecture.
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pageLevels = 4
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// ptePhysPageMask is a mask that allows us to extract the physical memory
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// address pointed to by a page table entry. For this particular architecture,
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// bits 12-51 contain the physical memory address.
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ptePhysPageMask = uintptr(0x000ffffffffff000)
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// tempMappingAddr is a reserved virtual page address used for
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// temporary physical page mappings (e.g. when mapping inactive PDT
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// pages). For amd64 this address uses the following table indices:
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// 510, 511, 511, 511.
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tempMappingAddr = uintptr(0Xffffff7ffffff000)
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)
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var (
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// pdtVirtualAddr is a special virtual address that exploits the
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// recursive mapping used in the last PDT entry for each page directory
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// to allow accessing the PDT (P4) table using the system's MMU address
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// translation mechanism. By setting all page level bits to 1 the MMU
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// keeps following the last P4 entry for all page levels landing on the
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// P4.
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pdtVirtualAddr = uintptr(math.MaxUint64 &^ ((1 << 12) - 1))
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// pageLevelBits defines the number of virtual address bits that correspond to each
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// page level. For the amd64 architecture each PageLevel uses 9 bits which amounts to
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// 512 entries for each page level.
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pageLevelBits = [pageLevels]uint8{
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9,
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9,
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9,
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9,
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}
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// pageLevelShifts defines the shift required to access each page table component
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// of a virtual address.
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pageLevelShifts = [pageLevels]uint8{
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39,
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30,
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21,
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12,
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}
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)
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const (
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// FlagPresent is set when the page is available in memory and not swapped out.
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FlagPresent PageTableEntryFlag = 1 << iota
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// FlagRW is set if the page can be written to.
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FlagRW
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// FlagUserAccessible is set if user-mode processes can access this page. If
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// not set only kernel code can access this page.
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FlagUserAccessible
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// FlagWriteThroughCaching implies write-through caching when set and write-back
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// caching if cleared.
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FlagWriteThroughCaching
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// FlagDoNotCache prevents this page from being cached if set.
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FlagDoNotCache
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// FlagAccessed is set by the CPU when this page is accessed.
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FlagAccessed
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// FlagDirty is set by the CPU when this page is modified.
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FlagDirty
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// FlagHugePage is set if when using 2Mb pages instead of 4K pages.
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FlagHugePage
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// FlagGlobal if set, prevents the TLB from flushing the cached memory address
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// for this page when the swapping page tables by updating the CR3 register.
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FlagGlobal
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// FlagCopyOnWrite is used to implement copy-on-write functionality. This
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// flag and FlagRW are mutually exclusive.
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FlagCopyOnWrite = 1 << 9
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// FlagNoExecute if set, indicates that a page contains non-executable code.
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FlagNoExecute = 1 << 63
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)
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