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https://github.com/taigrr/gopher-os
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56d23f50ae
If the WP bit in CR0 is not set then write protection for pages is only enforced for user-land code.
365 lines
11 KiB
ArmAsm
365 lines
11 KiB
ArmAsm
; vim: set ft=nasm :
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%include "constants.inc"
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section .data
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align 4
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; GDT definition
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gdt0:
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gdt0_nil_seg: dw 0 ; Limit (low)
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dw 0 ; Base (low)
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db 0 ; Base (middle)
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db 0 ; Access (exec/read)
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db 0 ; Granularity
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db 0 ; Base (high)
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gdt0_cs_seg: dw 0 ; Limit (low)
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dw 0 ; Base (low)
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db 0 ; Base (middle)
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db 10011010b ; Access (exec/read)
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db 00100000b ; Granularity
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db 0 ; Base (high)
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gdt0_ds_seg: dw 0 ; Limit (low)
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dw 0 ; Base (low)
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db 0 ; Base (middle)
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db 10010010b ; Access (read/write)
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db 00000000b ; Granularity
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db 0 ; Base (high)
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gdt0_desc:
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dw $ - gdt0 - 1 ; gdt size should be 1 byte less than actual length
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dq gdt0 - PAGE_OFFSET
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NULL_SEG equ gdt0_nil_seg - gdt0
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CS_SEG equ gdt0_cs_seg - gdt0
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DS_SEG equ gdt0_ds_seg - gdt0
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;------------------------------------------------------------------------------
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; Error messages
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;------------------------------------------------------------------------------
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err_unsupported_bootloader db '[rt0_32] kernel not loaded by multiboot-compliant bootloader', 0
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err_multiboot_data_too_big db '[rt0_32] multiboot information data length exceeds local buffer size', 0
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err_cpuid_not_supported db '[rt0_32] the processor does not support the CPUID instruction', 0
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err_longmode_not_supported db '[rt0_32] the processor does not support longmode which is required by this kernel', 0
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err_sse_not_supported db '[rt0_32] the processor does not support SSE instructions which are required by this kernel', 0
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section .bss
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align 4096
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; Reserve 3 pages for the initial page tables
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page_table_l4: resb 4096
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page_table_l3: resb 4096
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page_table_l2: resb 4096
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; Reserve 16K for storing multiboot data and for the kernel stack
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global multiboot_data ; Make this available to the 64-bit entrypoint
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global stack_bottom
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global stack_top
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multiboot_data: resb 16384
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stack_bottom: resb 16384
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stack_top:
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section .rt0
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bits 32
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align 4
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;------------------------------------------------------------------------------
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; Kernel 32-bit entry point
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;
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; The boot loader will jump to this symbol after setting up the CPU according
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; to the multiboot standard. At this point:
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; - A20 is enabled
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; - The CPU is using 32-bit protected mode
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; - Interrupts are disabled
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; - Paging is disabled
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; - EAX contains the magic value ‘0x36d76289’; the presence of this value indicates
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; to the operating system that it was loaded by a Multiboot-compliant boot loader
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; - EBX contains the 32-bit physical address of the Multiboot information structure
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;------------------------------------------------------------------------------
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global _rt0_32_entry
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_rt0_32_entry:
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; Provide a stack
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mov esp, stack_top - PAGE_OFFSET
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; Ensure we were booted by a bootloader supporting multiboot
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cmp eax, 0x36d76289
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jne _rt0_32_entry.unsupported_bootloader
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; Copy multiboot struct to our own buffer
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call _rt0_copy_multiboot_data
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; Check processor features
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call _rt0_check_cpuid_support
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call _rt0_check_longmode_support
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call _rt0_check_sse_support
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; Setup initial page tables, enable paging and enter longmode
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call _rt0_populate_initial_page_tables
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call _rt0_enter_long_mode
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call _rt0_64_entry_trampoline
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.unsupported_bootloader:
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mov edi, err_unsupported_bootloader - PAGE_OFFSET
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call write_string
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jmp _rt0_32_entry.halt
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.halt:
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cli
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hlt
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;------------------------------------------------------------------------------
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; Copy multiboot information blocks from the address pointed to by ebx into a
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; local buffer. This enables the kernel code to access them once paging is enabled.
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;------------------------------------------------------------------------------
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_rt0_copy_multiboot_data:
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mov esi, ebx
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mov edi, multiboot_data - PAGE_OFFSET
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mov ecx, dword [esi]
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cmp ecx, 16384
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jle _rt0_copy_multiboot_data.copy
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mov edi, err_multiboot_data_too_big - PAGE_OFFSET
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call write_string
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jmp _rt0_32_entry.halt
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.copy:
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test ecx, ecx
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jz _rt0_copy_multiboot_data.done
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mov eax, dword[esi]
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mov dword [edi], eax
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add esi, 4
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add edi, 4
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sub ecx, 4
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jmp _rt0_copy_multiboot_data.copy
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.done:
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ret
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;------------------------------------------------------------------------------
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; Check that the processor supports the CPUID instruction.
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;
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; To check if CPUID is supported, we need to attempt to flip the ID bit (bit 21)
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; in the FLAGS register. If that works, CPUID is available.
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;
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; Code taken from: http://wiki.osdev.org/Setting_Up_Long_Mode#x86_or_x86-64
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;------------------------------------------------------------------------------
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_rt0_check_cpuid_support:
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; Copy FLAGS in to EAX via stack
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pushfd
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pop eax
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; Copy to ECX as well for comparing later on
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mov ecx, eax
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; Flip the ID bit
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xor eax, 1 << 21
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; Copy EAX to FLAGS via the stack
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push eax
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popfd
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; Copy FLAGS back to EAX (with the flipped bit if CPUID is supported)
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pushfd
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pop eax
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; Restore FLAGS from the old version stored in ECX (i.e. flipping the
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; ID bit back if it was ever flipped).
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push ecx
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popfd
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; Compare EAX and ECX. If they are equal then that means the bit
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; wasn't flipped, and CPUID isn't supported.
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cmp eax, ecx
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je _rt0_check_cpuid_support.no_cpuid
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ret
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.no_cpuid:
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mov edi, err_cpuid_not_supported - PAGE_OFFSET
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call write_string
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jmp _rt0_32_entry.halt
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;------------------------------------------------------------------------------
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; Check that the processor supports long mode
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; Code taken from: http://wiki.osdev.org/Setting_Up_Long_Mode#x86_or_x86-64
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;------------------------------------------------------------------------------
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_rt0_check_longmode_support:
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; To check for longmode support we need to ensure that the CPUID instruction
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; can report it. To do this we need to query it first.
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mov eax, 0x80000000 ; Set the A-register to 0x80000000.
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cpuid
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cmp eax, 0x80000001 ; We need at least 0x80000001 to check for long mode.
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jb _rt0_check_longmode_support.no_long_mode
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mov eax, 0x80000001 ; Set the A-register to 0x80000001.
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cpuid
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test edx, 1 << 29 ; Test if the LM-bit, which is bit 29, is set in the D-register.
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jz _rt0_check_longmode_support.no_long_mode
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ret
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.no_long_mode:
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mov edi, err_longmode_not_supported - PAGE_OFFSET
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call write_string
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jmp _rt0_32_entry.halt
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;------------------------------------------------------------------------------
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; Check for and enabl SSE support. Code taken from:
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; http://wiki.osdev.org/SSE#Checking_for_SSE
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;------------------------------------------------------------------------------
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_rt0_check_sse_support:
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; check for SSE
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mov eax, 0x1
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cpuid
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test edx, 1<<25
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jz _rt0_check_sse_support.no_sse
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; Enable SSE
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mov eax, cr0
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and ax, 0xfffb ; Clear coprocessor emulation CR0.EM
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or ax, 0x2 ; Set coprocessor monitoring CR0.MP
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mov cr0, eax
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mov eax, cr4
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or ax, 3 << 9 ; Set CR4.OSFXSR and CR4.OSXMMEXCPT at the same time
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mov cr4, eax
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ret
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.no_sse:
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mov edi, err_sse_not_supported - PAGE_OFFSET
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call write_string
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jmp _rt0_32_entry.halt
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;------------------------------------------------------------------------------
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; Setup minimal page tables to allow access to the following regions:
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; - 0 to 8M
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; - PAGE_OFFSET to PAGE_OFFSET + 8M
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;
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; The second region mapping allows us to access the kernel at its VMA when
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; paging is enabled.
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;------------------------------------------------------------------------------
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PAGE_PRESENT equ (1 << 0)
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PAGE_WRITABLE equ (1 << 1)
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PAGE_2MB equ (1 << 7)
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_rt0_populate_initial_page_tables:
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; The CPU uses bits 39-47 of the virtual address as an index to the P4 table.
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mov eax, page_table_l3 - PAGE_OFFSET
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or eax, PAGE_PRESENT | PAGE_WRITABLE
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mov ebx, page_table_l4 - PAGE_OFFSET
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mov [ebx], eax
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; Recursively map the last P4 entry to itself. This allows us to use
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; specially crafted memory addresses to access the page tables themselves
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mov ecx, ebx
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or ecx, PAGE_PRESENT | PAGE_WRITABLE
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mov [ebx + 511*8], ecx
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; Also map the addresses starting at PAGE_OFFSET to the same P3 table.
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; To find the P4 index for PAGE_OFFSET we need to extract bits 39-47
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; of its address.
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mov ecx, (PAGE_OFFSET >> 39) & 511
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mov [ebx + ecx*8], eax
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; The CPU uses bits 30-38 as an index to the P3 table. We just need to map
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; entry 0 from the P3 table to point to the P2 table .
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mov eax, page_table_l2 - PAGE_OFFSET
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or eax, PAGE_PRESENT | PAGE_WRITABLE
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mov ebx, page_table_l3 - PAGE_OFFSET
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mov [ebx], eax
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; For the L2 table we enable the huge page bit which allows us to specify
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; 2M pages without needing to use the L1 table. To cover the required
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; 0-8M region we need to provide 4 2M page entries at indices 0 to 4.
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mov ecx, 0
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mov ebx, page_table_l2 - PAGE_OFFSET
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.next_page:
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mov eax, 1 << 21 ; 2M
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mul ecx ; eax *= ecx
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or eax, PAGE_PRESENT | PAGE_WRITABLE | PAGE_2MB
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mov [ebx + ecx*8], eax
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inc ecx
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cmp ecx, 4
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jne _rt0_populate_initial_page_tables.next_page
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ret
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;------------------------------------------------------------------------------
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; Load P4 table, enable PAE, enter long mode and finally enable paging
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;------------------------------------------------------------------------------
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_rt0_enter_long_mode:
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; Load page table map pointer to cr3
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mov eax, page_table_l4 - PAGE_OFFSET
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mov cr3, eax
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; Enable PAE support
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mov eax, cr4
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or eax, 1 << 5
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mov cr4, eax
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; Now enable long mode (bit 8) and the no-execute support (bit 11) by
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; modifying the EFER MSR
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mov ecx, 0xc0000080
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rdmsr ; read msr value to eax
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or eax, (1 << 8) | (1<<11)
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wrmsr
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; Finally enable paging (bit 31) and user/kernel page write protection (bit 16)
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mov eax, cr0
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or eax, (1 << 31) | (1<<16)
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mov cr0, eax
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; We are in 32-bit compatibility submode. We need to load a 64bit GDT
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; and perform a far jmp to switch to long mode
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mov eax, gdt0_desc - PAGE_OFFSET
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lgdt [eax]
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; set ds and es segments
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; to set the cs segment we need to perform a far jmp
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mov ax, DS_SEG
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mov ds, ax
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mov es, ax
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mov fs, ax
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mov gs, ax
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mov ss, ax
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jmp CS_SEG:.flush_gdt - PAGE_OFFSET
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.flush_gdt:
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ret
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;------------------------------------------------------------------------------
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; Write the NULL-terminated string contained in edi to the screen using white
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; text on red background. Assumes that text-mode is enabled and that its
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; physical address is 0xb8000.
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;------------------------------------------------------------------------------
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write_string:
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mov ebx,0xb8000
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mov ah, 0x4F
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.next_char:
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mov al, byte[edi]
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test al, al
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jz write_string.done
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mov word [ebx], ax
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add ebx, 2
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inc edi
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jmp write_string.next_char
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.done:
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ret
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;------------------------------------------------------------------------------
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; Set up the stack pointer to the virtual address of the stack and jump to the
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; 64-bit entrypoint.
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;------------------------------------------------------------------------------
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bits 64
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_rt0_64_entry_trampoline:
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mov rsp, stack_top ; now that paging is enabled we can load the stack
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; with the virtual address of the allocated stack.
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; Jump to 64-bit entry
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extern _rt0_64_entry
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mov rax, _rt0_64_entry
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jmp rax
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