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Achilleas Anagnostopoulos 5a2efb2bd3 Load IDT and define gate error-code-aware handlers (rt0/x86_64)

The rt0_64 code will load a blank IDT with 256 entries (the max number
of supported interrupts in the x86_64 architecture). Each IDT entry is
set as *not present* but its handler is set to a dedicated gate entrypoint
defined in the rt0 code.

A gate entrypoint is defined for each interrupt number using a nasm
macro. Each entrypoint will then use the interrupt number to index a
list of pointers (defined and managed by the Go assembly code in
the irq pkg) to the registered interrupt handlers and push its address
on the stack before jumping to one of the two available gate dispatching
functions (some interrupts also push an error code to the stack which
must be popped before returning from the interrupt handler):
- _rt0_64_gate_dispatcher_with_code
- _rt0_64_gate_dispatcher_without_code

Both dispatchers operate in the same way:
- they save the original registers
- they invoke the interrupt handler
- they restore the original registers
- ensure that the stack pointer (rsp) points to the exception frame
  pushed by the CPU

The difference between the dispatchers is that the "with_code" variant
will invoke a handler with signature `func(code, &frame, &regs)` and
ensure that the code is popped off the stack before returning from the
interrupt while the "without_code" variant will invoke a handler with
signature `func(&frame, &regs)`

2017-06-21 17:46:41 +01:00

arch/x86_64

Load IDT and define gate error-code-aware handlers (rt0/x86_64)

2017-06-21 17:46:41 +01:00

kernel

Add assemnly code for enabling/disabling insterrupts and halting the CPU

2017-06-21 07:59:48 +01:00

.gitignore

Update .gitignore

2017-03-23 06:50:13 +00:00

.travis.yml

Add lint Makefile target